DocumentCode
1914312
Title
Testing of critical paths for delay faults
Author
Sharma, Manish ; Patel, Janak H.
Author_Institution
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
fYear
2001
fDate
2001
Firstpage
634
Lastpage
641
Abstract
Testing the critical paths in a circuit is essential to cover distributed delay and small delay defects in a manufactured circuit. However, in most circuits, only a small percentage of functionally irredundant critical paths (which can affect the cycle time) are robustly testable. We propose the covering of defects on untestable critical paths by robustly testing the longest testable segments lying on those paths. This method is scalable to large circuits since the task of segment delay fault test generation has complexity similar to path delay fault test generation. Experimental results have been given to demonstrate that significant additional coverage of defects on critical paths can be achieved using this technique
Keywords
automatic test pattern generation; automatic testing; combinational circuits; delays; fault diagnosis; logic testing; timing; ISCAS combinational benchmark circuits; critical paths; cycle time; delay defects; distributed delay; functionally irredundant paths; logic behavior; longest testable segments; segment delay fault test generation; timing violation; Benchmark testing; Circuit faults; Circuit testing; Delay; High performance computing; Integrated circuit testing; Logic testing; Manufacturing; Robustness; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2001. Proceedings. International
Conference_Location
Baltimore, MD
ISSN
1089-3539
Print_ISBN
0-7803-7169-0
Type
conf
DOI
10.1109/TEST.2001.966683
Filename
966683
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