Title :
CMOS Device Architecture and Technology for the 0.25 Micron to 0.025 Micron Generations
Author_Institution :
ULSI Labs., Toshiba Corp., Kawasaki, Japan
Abstract :
Device structures and technologies for high-speed logic CMOS LSIs have been reviewed, covering the range from several microns to the far future of 1/40 micron devices. The future 0.25 to 0.1 μm generation was investigated in detail. In this generation, optimum design of the impurity profile and fine control over impurity doping - to suppress short-channel effects and to minimize the series source/drain resistance - will be the critical issues. New doping techniques will need to be developed to meet the requirements. Intelligent CAD systems which are able to create an optimum interconnect design for high-speed operation will become indispensable, as will highly reliable circuits. For the sub-tenth micron range, undoped epitaxial channel MOSFETs and double-gate SOI MOSFETs appear to be most promising, and correct operation of these devices was confirmed through simulations. However, no concept of a realistic ULSI based on these transistors is available at this point.
Keywords :
CMOS logic circuits; MOSFET; electronic design automation; integrated circuit interconnections; large scale integration; silicon-on-insulator; CMOS device architecture; double-gate SOI MOSFET; high-speed operation; impurity doping; impurity profile; intelligent CAD system; logic CMOS LSI; optimum design; optimum interconnect design; size 0.25 mum to 0.025 mum; undoped epitaxial channel MOSFET; CMOS logic circuits; CMOS process; CMOS technology; Integrated circuit interconnections; Large scale integration; Logic devices; MOSFETs; Rapid thermal annealing; Thermal resistance; Wiring;
Conference_Titel :
Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European
Conference_Location :
Grenoble
