VLSI design of an ATM switch with automatic fault detection

Author

Kwan, Louis Chung-Yin ; Tsui, Chi-ying ; Lea, Chin-Tau

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Clear Water Bay, Hong Kong

Volume

6

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

478

Abstract

This paper describes a VLSI implementation of a multistage self-routing ATM switch fabric. The size of the switch prototype is 16×16 and is designed to handle the OC-12 (622 Mbps) link rate. Based on a bit-slice architecture, the entire 16×16 switch is implemented using four identical chips. The switch has multiple paths, created by a randomizer in front of the routing stages, between each input-output pair. The switch uses an input/output-buffering scheme and contains no buffers inside the fabric. To facilitate fault detection and isolation, we add automatic fault detection schemes at the node, chip, and system levels of the design

Keywords

VLSI; asynchronous transfer mode; electronic switching systems; fault diagnosis; 622 Mbit/s; OC-12 link; VLSI design; automatic fault detection; bit-slice architecture; fault isolation; multistage self-routing ATM switch; Asynchronous transfer mode; Centralized control; Electrical fault detection; Fabrics; Fault detection; Routing; Switches; Throughput; Traffic control; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.705315

Filename

705315