Title :
An analysis of power reduction techniques in scan testing
Author :
Saxena, Jayashree ; Butler, Kenneth M. ; Whetsel, Lee
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
Power consumption during scan testing is becoming a concern. Circuit switching activity during scan shifting is high and results in high average and instantaneous power consumption. This paper presents a scheme for reducing power and provides analysis results on an industrial design
Keywords :
automatic test pattern generation; boundary scan testing; clocks; decoding; integrated circuit testing; logic testing; low-power electronics; ATPG; average power consumption; circuit switching activity; clock gating; combinational switching activity; decoding logic; industrial design; instantaneous power consumption; power reduction techniques; scan shifting; scan testing; Capacitance; Circuit testing; Clocks; Counting circuits; Energy consumption; Flip-flops; Frequency; Logic; Shift registers; Switching circuits;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966687
