DocumentCode
1914497
Title
A study of bridging defect probabilities on a Pentium (TM) 4 CPU
Author
Krishnaswamy, V. ; Ma, A.B. ; Vishakantaiah, P.
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
2001
fDate
2001
Firstpage
688
Lastpage
695
Abstract
Presents an experimental study of bridging fault locations on the Intel Pentium (TM) 4 CPU as determined by an inductive fault analysis tool. The study focuses on the location and distribution of probable bridging defects and attempts to explain the findings in the context of the characteristics of the design and its implementation. The coverage obtained against these faults by manually generated functional patterns is compared against that achieved by ATPG vectors
Keywords
CMOS digital integrated circuits; VLSI; automatic test pattern generation; fault simulation; integrated circuit testing; microprocessor chips; production testing; ATPG vectors; CMOS; Pentium 4 CPU; VLSI; bridging defect probabilities; defect behaviors; fault models; inductive fault analysis tool; manually generated functional patterns; manufacturing testing; Automatic test pattern generation; CMOS process; Circuit faults; Circuit testing; Electrical fault detection; Fabrication; Fault location; Semiconductor device modeling; Test pattern generators; Virtual manufacturing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2001. Proceedings. International
Conference_Location
Baltimore, MD
ISSN
1089-3539
Print_ISBN
0-7803-7169-0
Type
conf
DOI
10.1109/TEST.2001.966689
Filename
966689
Link To Document