Using artificial neural networks to improve hardware branch predictors

Among the current techniques to predict the outcome of branches in modern microprocessors, two-level branch predictors have shown to be one of the best mechanisms. The correct prediction of branches is a fundamental factor for achieving high performance. Branch interference is a major contributor to the number of branches mispredicted by two-level predictors. Increasing the size of the pattern history table (PHT) reduces the interference, but the number of transistors that can be assigned to the PHT and the frequency at which it can be accessed limits the increase on its size. Another method for reducing interference is that of the gshare predictor. The gshare predictor combines the information used to generate the index into the PHT to increase its efficiency. In this paper, neural networks are used to discover a prediction algorithm to reduce interference and therefore increase the performance of two-level branch predictors. The neural net learns about the dynamics of programs to be executed in a microprocessor. A table of comparative performance with other established prediction methods is provided