DocumentCode
1914562
Title
Chemical Mechanical Polishing for Planarisation of Advanced IC Processes
Author
Lifka, H. ; Doedel, W. ; Souts, T. ; Woerlee, P.H.
Author_Institution
Philips Res. Labs., Eindhoven, Netherlands
fYear
1993
fDate
13-16 Sept. 1993
Firstpage
557
Lastpage
560
Abstract
An CMP process will be presented which is optimised for low layout sensitivity and good uniformity. The best results were obtained by using a stack of two polishing cloths, instead of a single cloth. This results in a better planarisation capability while improving the uniformity compared to a single hard polishing cloth. The feasibility of the novel CMP process was demonstrated on a 64k SRAM.
Keywords
SRAM chips; chemical mechanical polishing; elemental semiconductors; integrated circuits; planarisation; silicon; 64k SRAM; Si; advanced IC process; chemical mechanical polishing; low layout sensitivity; planarisation; two polishing cloths; Bonding; Chemical processes; Circuits; Dry etching; Laboratories; Lithography; Planarization; Random access memory; Silicon; Surface topography;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European
Conference_Location
Grenoble
Print_ISBN
2863321358
Type
conf
Filename
5435562
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