Title :
Scan test sequencing hardware for structural test
Author_Institution :
Schlumberger Semicond. Solutions, San Jose, CA, USA
Abstract :
This paper introduces a new hardware implementation for scan test sequencing within a tester. Instead of providing a monolithic scan memory with linear readback capabilities, the proposed test architecture uses dedicated scan test sequencing hardware to provide "on-the-fly" scan test sequencing. The approach is aimed not only at providing a more flexible test hardware solution, but at reducing the cost of structural test by significantly reducing scan memory size requirements
Keywords :
automatic test equipment; boundary scan testing; integrated circuit testing; IP cores; flexible test hardware solution; hardware implementation; linear test ture; on-the-fly scan test sequencing; scan memory size requirements; scan test sequencing hardware; structural test; Clocks; Costs; Filters; Hardware; Integrated circuit testing; Interleaved codes; Production; Semiconductor device testing; Sequential analysis; System testing;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966692
