A Floorprint-based Defect Tolerance for Nano-scale Application-Specific IC

Author

Ahn, S. ; Patitz, Z. ; Park, N.

Author_Institution

Dept. of Comput. Sci., Korea Mil. Acad., Seoul

fYear

2008

fDate

12-15 May 2008

Firstpage

1839

Lastpage

1844

Abstract

A floorprint-based yield modeling, assurance and optimization method for the defect tolerant NASIC system under broken NW defects is proposed and validated through extensive parametric simulations in this paper. Ultimately, intelligent exploitation of the proposed yield modeling and simulation methods will make possible to realize a reliable NASIC-based computing system. According to the simulation results given in this paper, the defect tolerant NASIC system with 15 row and column NWs, respectively, each with length = 0.000034 on horizontal and vertical core nanoarray in a nanotile can achieve a yield higher than 99.8%.

Keywords

application specific integrated circuits; circuit optimisation; integrated circuit yield; nanoelectronics; NASIC-based computing system; floorprint-based defect tolerance; intelligent exploitation; nanoscale application-specific IC; optimization method; parametric simulations; vertical core nanoarrays; Application specific integrated circuits; CMOS technology; Circuit faults; Circuits and systems; Computational modeling; Computer science; Economic forecasting; Nanoelectronics; Nanoscale devices; Redundancy; Defect tolerance; NASIC; floorprint;

fLanguage

English

Publisher

ieee

Conference_Titel

Instrumentation and Measurement Technology Conference Proceedings, 2008. IMTC 2008. IEEE

Conference_Location

Victoria, BC

ISSN

1091-5281

Print_ISBN

978-1-4244-1540-3

Electronic_ISBN

1091-5281

Type

conf

DOI

10.1109/IMTC.2008.4547344

Filename

4547344