DocumentCode :
1914689
Title :
OPMISR: the foundation for compressed ATPG vectors
Author :
Barnhart, Carl ; Brunkhorst, Vanessa ; Distler, Frank ; Farnsworth, Owen ; Keller, Brion ; Koenemann, Bernd
Author_Institution :
IBM Microelectron., Tucson, AZ, USA
fYear :
2001
fDate :
2001
Firstpage :
748
Lastpage :
757
Abstract :
Rapid increases in the wire-able gate counts of ASICs stress existing manufacturing test equipment in terms of test data volume and test capacity. Techniques are presented in this paper that allow for substantial compression of Automatic Test Pattern Generation (ATPG) produced test vectors. We show compression efficiencies allowing a more than 10-fold reduction in tester scan buffer data volume on ATPG compacted tests. In addition, we obtain almost a 2× scan test time reduction. By implementing these techniques for production testing of huge-gate-count ASICs, IBM will continue using existing automated test equipment (ATE)-avoiding costly upgrades and replacements
Keywords :
application specific integrated circuits; automatic test equipment; automatic test pattern generation; design for testability; integrated circuit testing; logic testing; production testing; ASICs; ATE; DFT; IBM; OPMISR; compressed ATPG vectors; compression efficiencies; huge-gate-count ASICs; on-product multiple-input signature register; production testing; scan test time reduction; scan-based logic testing; test capacity; test data volume; tester scan buffer data volume; wire-able gate counts; Amplitude shift keying; Application specific integrated circuits; Automatic test pattern generation; Automatic testing; Circuit testing; Costs; Logic testing; Manufacturing; Pins; Test equipment;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
ISSN :
1089-3539
Print_ISBN :
0-7803-7169-0
Type :
conf
DOI :
10.1109/TEST.2001.966696
Filename :
966696
Link To Document :
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