Analytic modeling of gate tunneling currents for nano-scale double-gate MOSFETs

The gate tunneling currents that are present in double-gate fully depleted fin-shaped MOSFETs either with a single high-k layer or a SiO₂/high-k stack as gate dielectric material are modeled, in order to define its contributions to the total measured gate leakage current at different gate bias conditions. Direct tunneling of electrons from Si conduction band provided by all the channel region at strong inversion conditions and trap-assisted tunneling effect at the overlaps in subthreshold regime have been taken into account in order to represent correctly the behavior of gate leakage current in state-of-art devices. By using simple analytic expressions, this model shows an excellent agreement with measured gate I-V characteristics from depletion to strong inversion operation modes.