Title :
Analytic modeling of gate tunneling currents for nano-scale double-gate MOSFETs
Author :
Garduño, Salvador I. ; Cerdeira, A. ; Estrada, M. ; Kylchitska, V. ; Flandre, D.
Author_Institution :
Dept. of Electr. Eng., CINVESTAV, Mexico City, Mexico
Abstract :
The gate tunneling currents that are present in double-gate fully depleted fin-shaped MOSFETs either with a single high-k layer or a SiO2/high-k stack as gate dielectric material are modeled, in order to define its contributions to the total measured gate leakage current at different gate bias conditions. Direct tunneling of electrons from Si conduction band provided by all the channel region at strong inversion conditions and trap-assisted tunneling effect at the overlaps in subthreshold regime have been taken into account in order to represent correctly the behavior of gate leakage current in state-of-art devices. By using simple analytic expressions, this model shows an excellent agreement with measured gate I-V characteristics from depletion to strong inversion operation modes.
Keywords :
MOSFET; high-k dielectric thin films; leakage currents; nanoelectronics; silicon compounds; tunnelling; SiO2; channel region; direct electron tunneling; double-gate fully depleted fin-shaped MOSFET; gate I-V characteristics; gate bias condition; gate dielectric material; gate leakage current; gate tunneling current; high-k layer; high-k stack; nanoscale double-gate MOSFET; subthreshold regime; trap-assisted tunneling effect; Dielectrics; FinFETs; Leakage current; Logic gates; Silicon; Tunneling; direct tunneling gate current model; double-gate MOSFET model; trap-assisted tunneling current model;
Conference_Titel :
Devices, Circuits and Systems (ICCDCS), 2012 8th International Caribbean Conference on
Conference_Location :
Playa del Carmen
Print_ISBN :
978-1-4577-1116-9
Electronic_ISBN :
978-1-4577-1115-2
DOI :
10.1109/ICCDCS.2012.6188938
