Bitline contacts in high density SRAMs: design for testability and stressability

Process scaling and the need for smaller SRAM cells challenges process technologies to make millions of robust and reliable bitline contacts on a single chip. Another challenge is to identify marginal, resistive and unreliable bitline contacts given the inherent electrical characteristics of the SRAM cell. This paper describes two design techniques that improve the screenability and stressability of bitline contacts in high-density SRAMs. These techniques are developed to overcome the lack of detectability of resistive bitline contacts in SRAM cells