Boundary-Scan Interconnect Test Vector Generation During VHDL Synthesis

Author

Olozábal, Ángle Quirós ; Vela, Diego Gómez ; Chacón, Ma de los Ángeles Cifredo ; Rodríguez, José María Guerrero ; Villar, Juan Manuel Barrientos

Author_Institution

Microelectron. Design Group, Cadiz Univ.

Volume

1

fYear

2005

fDate

21-24 Nov. 2005

Firstpage

495

Lastpage

498

Abstract

In this paper we present a group of VHBL functions that generate the interconnection test vectors for a boundary-scan board. The functions are part of a synthesizable VHDL model for a boundary-scan tester, and they obtain the vectors to be sent to the boundary-scan chain, to be received from it, and to enable the evaluation of the received response. The information needed by these functions are the boundary-scan data of the components of the board and a description of the interconnections between the cells. Using these functions the synthesis tool generates the vectors without needing any other external automatic-test-pattern-generation (ATPG) program

Keywords

automatic test pattern generation; boundary scan testing; hardware description languages; logic testing; VHDL synthesis; automatic test pattern generation; boundary-scan board; interconnection test vectors; synthesis tool; vector generation; Testing; ATPG; Boundary-Scan; Synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer as a Tool, 2005. EUROCON 2005.The International Conference on

Conference_Location

Belgrade

Print_ISBN

1-4244-0049-X

Type

conf

DOI

10.1109/EURCON.2005.1629973

Filename

1629973