Boundary-Scan Interconnect Test Vector Generation During VHDL Synthesis

In this paper we present a group of VHBL functions that generate the interconnection test vectors for a boundary-scan board. The functions are part of a synthesizable VHDL model for a boundary-scan tester, and they obtain the vectors to be sent to the boundary-scan chain, to be received from it, and to enable the evaluation of the received response. The information needed by these functions are the boundary-scan data of the components of the board and a description of the interconnections between the cells. Using these functions the synthesis tool generates the vectors without needing any other external automatic-test-pattern-generation (ATPG) program