Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs

Author

Al-Ars, Zaid ; Van de Goor, Ad J. ; Braun, Jens ; Richter, Detlev

Author_Institution

Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands

fYear

2001

fDate

2001

Firstpage

783

Lastpage

792

Abstract

Temperature has proven to be an effective stress condition, commonly used to stress memory devices and to detect special types of failure mechanisms. In this paper a new approach is presented where temperature is used as a test parameter to increase the fault coverage of specific tests. This is done using defect injection and simulation of a memory model at different temperatures. The analysis presents new types of detection conditions for memories and evaluates the impact of temperature on these conditions

Keywords

DRAM chips; SPICE; circuit simulation; embedded systems; failure analysis; fault location; integrated circuit testing; logic testing; thermal stresses; Spice; defect injection; defect simulation; embedded DRAM; failure mechanisms; fault coverage; fault primitives; functional fault models; memory model; memory testing; opens; stress condition; stress memory devices; temperature effect; test parameter; Analytical models; Circuit faults; Circuit simulation; Computational modeling; Failure analysis; Information technology; Random access memory; Stress; Temperature; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2001. Proceedings. International

Conference_Location

Baltimore, MD

ISSN

1089-3539

Print_ISBN

0-7803-7169-0

Type

conf

DOI

10.1109/TEST.2001.966700

Filename

966700