A Comparative Analysis of a Distributed On-Chip RLC Interconnect Model under Ramp Excitation

The continuous down scaling of feature sizes into deep sub-micrometer dimensions, coupled with the used of high operation frequency in very large scale integration (VLSI) has made the on-chip interconnect the most dominant factor determining the overall circuit signal integrity performance. However, present VLSI interconnects are best modelled as distributed RLC lines. Thus, the generally well-accepted and popular Elmore delay estimation model becomes inapplicable for present integrated circuits (ICs). In this paper, we present two different closed-form analytical models for estimating the time-delay of a distributed RLC interconnect. Simulation results show that both models are quite accurate when compared to simulation results from SPICE. The choice of a particular approach is also discussed and is mainly dependent on the trade-off between accuracy and complexity