Path Optimization Protocol Based on Speed Low Power Metrics

The design of high performance circuits implies to manage CAD tools with physical level defined indicators. In this paper, we validate a design space exploration method, defining maximum and minimum delay bounds on logical paths. Then we adapt this method to a "constant sensitivity method" allowing to size a circuit at minimum area under a delay constraint. Three techniques are characterized: path global sizing, local buffer insertion and mixed sizing and buffer insertion. These methods are implemented in an optimization tool and compared on ISCAS\´85 benchmarks with an industrial tool