A Physically Based DC-and AC-Model for Vertical Smart Power DMOS Transistors

Based on device simulations an analytical DC- and AC-model for vertical DMOS transistors has been developed. It is based on a subcircuit approach. An enhanced MOS model for the channel and an adapted JFET model which accounts for drift velocity saturation in the drift region are used. As in existing approaches both the nonconstant doping in the channel region and the AC-behavior of the DMOS have not been thoroughly investigated special attention is paid to these aspects. Comparisons with numerical device simulations are presented to confirm the physical correctness of the new approaches.