• DocumentCode
    1914973
  • Title

    Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations

  • Author

    Mariniello, Genaro ; Doria, Rodrigo Trevisoli ; De Souza, Michelly ; Pavanello, Marcelo Antonio ; Trevisoli, Ranan Doria

  • Author_Institution
    Dept. of Electr. Eng., Centro Univ. da FEI, Sao Bernardo do Campo, Brazil
  • fYear
    2012
  • fDate
    14-17 March 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Junctionless transistors can be an excellent alternative for extremely scaled MOSFETs as they present a good behavior with no doping gradients between channel and source/drain regions. This paper aims at analyzing the gate capacitance (Cgg) of junctionless transistors dependence with the three most important technological parameters for these devices: doping concentration (ND), fin width (Wfin) and fin height (Hfin).
  • Keywords
    MOSFET; semiconductor device models; semiconductor doping; doping concentration; doping gradients; extremely scaled MOSFET; fin height; fin width; gate capacitance; n-type junctionless transistors; three-dimensional device simulations; Conferences; Gate Capacitance; Junctionless Devices;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Devices, Circuits and Systems (ICCDCS), 2012 8th International Caribbean Conference on
  • Conference_Location
    Playa del Carmen
  • Print_ISBN
    978-1-4577-1116-9
  • Electronic_ISBN
    978-1-4577-1115-2
  • Type

    conf

  • DOI
    10.1109/ICCDCS.2012.6188946
  • Filename
    6188946
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1914973