Performance Evaluation of a Noise Canceller Filter to be used in Codesign Techniques

Author

De Icaya, E. Martinez ; Rodellar, V. ; Peinado, V. ; Garcia, V. ; Diaz, A. ; Lez, C. Gonza

Author_Institution

Sch. of Comput. Sci., Univ. Politecnica de Madrid

Volume

1

fYear

2005

fDate

21-24 Nov. 2005

Firstpage

543

Lastpage

546

Abstract

Codesign techniques allow exploring different design alternatives at the system level specification by means of realizations in hardware and software for each composing blocks, and thus to evaluate the system performance before choosing the final implementation. In this paper the performance estimation in terms of area, time and power dissipation of a noise canceller filter both in software and hardware implementations is presented. The approximation has consisted of the specification of the problem in ANSI C and its transformation through synthesis tools into assembler code for the DSP 56000 microprocessor and into RTL VHDL synthesizable code by means of SPARK (S. Gupta et al., 2003). Also more precise hardware estimation for FPGA´s and standard cells is presented

Keywords

digital filters; field programmable gate arrays; hardware description languages; interference suppression; microprocessor chips; performance evaluation; ANSI C; DSP 56000 microprocessor; FPGA; RTL VHDL synthesizable code; SPARK; assembler code; code generation; codesign technique; high level synthesis; noise canceller filter; performance evaluation; synthesis tools; system level specification; Assembly; Digital signal processing; Filters; Hardware; Microprocessors; Noise cancellation; Power dissipation; Software performance; Sparks; System performance; Code Generation; Codesign; Estimation; High Level Synthesis; Noise Cancellation; Partitioning;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer as a Tool, 2005. EUROCON 2005.The International Conference on

Conference_Location

Belgrade

Print_ISBN

1-4244-0049-X

Type

conf

DOI

10.1109/EURCON.2005.1629985

Filename

1629985