A new methodology for improved tester utilization

Author

Khoche, Ajay ; Kapur, Rohit ; Armstrong, David ; Williams, T.W. ; Tegethoff, Mick ; Rivoir, Jochen

Author_Institution

Agilent Technol. Inc., Palo Alto, CA, USA

fYear

2001

fDate

2001

Firstpage

916

Lastpage

923

Abstract

Typically the DFT features are decided during the design and remain fixed after the design is completed. This makes a device testable only on ATEs, which can satisfy the test requirements for that chip. If such an ATE is not available then the IC either cannot be fully tested, or ATE resources are wasted when it is designed for less capabilities. This paper presents a methodology that builds on the tester retargetable pattern technology for testing ICs on testers with different pin capabilities. Such a capability would be an essential element in reduced pin-count (multi-site) testing. The interfacing needs between the Test Automation World and the Tester Environment are also developed in this paper

Keywords

automatic test equipment; automatic test pattern generation; computer interfaces; design for testability; integrated circuit testing; reconfigurable architectures; ATE; DFT; interfacing; multi-site testing; reconfigurable scan chains; reduced pin-count testing; tester retargetable pattern technology; Automatic test pattern generation; Automatic testing; Automation; Circuit faults; Circuit testing; Design for testability; Integrated circuit technology; Integrated circuit testing; Pins; Shift registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2001. Proceedings. International

Conference_Location

Baltimore, MD

ISSN

1089-3539

Print_ISBN

0-7803-7169-0

Type

conf

DOI

10.1109/TEST.2001.966715

Filename

966715