BIST-based delay path testing in FPGA architectures

Author

Harris, Ian G. ; Menon, Premachandran R. ; Tessier, Russell

Author_Institution

Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA

fYear

2001

fDate

2001

Firstpage

932

Lastpage

938

Abstract

The widespread use of field programmable gate arrays (FPGAs) as components in high-performance systems has increased the significance of path delay faults in FPGAs. We present a technique for FPGA path delay fault detection which integrates test insertion with the FPGA placement and routing stages to accomplish testing with low test application time. An accurate static timing analyzer is used to identify critical paths and built-in self-test (BIST) hardware is inserted using a placement and routing tool. Initial experimental results show that testing is accomplished with low test application time for several benchmark designs

Keywords

built-in self test; delays; fault diagnosis; field programmable gate arrays; network routing; timing; BIST-based delay path testing; FPGA architectures; benchmark designs; built-in self-test hardware; critical paths; high-performance systems; path delay faults; placement; routing; static timing analyzer; test application time; test insertion; Automatic testing; Built-in self-test; Computer architecture; Delay; Field programmable gate arrays; Hardware; Logic testing; Reconfigurable logic; Routing; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2001. Proceedings. International

Conference_Location

Baltimore, MD

ISSN

1089-3539

Print_ISBN

0-7803-7169-0

Type

conf

DOI

10.1109/TEST.2001.966717

Filename

966717