Analysis of Carrier Transport and Heating in Ultra-Small SOI N-MOSFETs

Author

Fiegna, C. ; Iwai, H. ; Sangiorgi, E. ; Riccò, B.

Author_Institution

ULSI Labs., Toshiba Corp., Kawasaki, Japan

fYear

1993

fDate

13-16 Sept. 1993

Firstpage

675

Lastpage

678

Abstract

Device simulation is adopted to investigate the main implications of scaling SOI MOSFETs to gate length well below 0.1μm. Effects of the reduction of silicon layer thickness and of the back oxide thickness are discussed. Reduction of the silicon layer thickness is effective in suppressing short channel effects (SCE) by ensuring better gate control of the back interface. Furthermore, the results of Monte Carlo simulations predict, in agreement with recent experiments, a decrease of hot carrier effects. On the other hand, by reducing the silicon layer thickness, an increase of the carrier transit time may be expected.

Keywords

MOSFET; Monte Carlo methods; heating; hot carriers; silicon; silicon-on-insulator; Monte Carlo simulations; Si; carrier transport; device simulation; gate length well; heating; hot carrier effects; reduction; short channel effects; silicon layer thickness; ultra-small SOI N-MOSFET; Analytical models; Heating; Hot carrier effects; Laboratories; MOSFET circuits; Research and development; Silicon; Thickness control; Tunneling; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European

Conference_Location

Grenoble

Print_ISBN

2863321358

Type

conf

Filename

5435586