Shadow write and read for at-speed BIST of TDM SRAMs

Time Domain Multiplex (TDM) SRAMs are a new type of multi-port SRAMs. Due to their small area and flexibility, they have found a wide range of applications in telecommunication ASICs. For a TDM SRAM, the memory core runs many times faster than the circuits that access it. In other words, the memory runs at an internal clock that is much faster than the system clock. This slow system clock coupled with the fast internal clock creates new challenges for at-speed testing of TDM SRAMs. This paper proposes a novel BIST solution for at-speed testing of TDM SRAMs with a slow system clock. The solution can be implemented with most commercial BIST controllers for conventional SRAMs. All the required modifications can be included in a modified memory collar The hardware addition is small. The test time is the same as that for a conventional multi-port SRAM of the same size