Title :
A Low-Power Phase-Locked Loop for UWB Applications
Author :
Rapinoja, Tapio ; Stadius, Kari ; Halonen, Kari
Author_Institution :
Electron. Circuit Design Lab., Helsinki Univ. of Technol.
Abstract :
This paper describes a low-power phase-locked loop (PLL) design for multiband-OFDM UWB synthesizer implemented in a 0.13-mum CMOS process. Three parallel PLLs and a multiplexer (MUX) constitute a frequency synthesizer which is used to generate carrier frequencies to UWB band groups 1 and 3. The implemented PLL consumes only 10 mW from a 1.2-V supply. Moreover, it achieves a close-in spurious tone level of -54 dBc and in-band phase noise of -78 dBc/Hz
Keywords :
CMOS integrated circuits; OFDM modulation; frequency synthesizers; low-power electronics; phase locked loops; ultra wideband technology; 0.13 micron; 1.2 V; 10 mW; CMOS process; UWB applications; carrier frequencies; frequency synthesizer; low-power phase-locked loop; multiband-OFDM UWB synthesizer; multiplexer; Bandwidth; Charge pumps; Filters; Frequency conversion; Frequency synthesizers; Multiplexing; Phase frequency detector; Phase locked loops; Switches; Voltage-controlled oscillators;
Conference_Titel :
Norchip Conference, 2006. 24th
Conference_Location :
Linkoping
Print_ISBN :
1-4244-0772-9
DOI :
10.1109/NORCHP.2006.329236
