DocumentCode
1915570
Title
An Energy-Efficient 32-bit Multiplier Architecture in 90-nm CMOS
Author
Mehmood, Nasir ; Hansson, Martin ; Alvandpour, Atila
Author_Institution
Dept. of Electr. Eng., Linkoping Univ.
fYear
2006
fDate
Nov. 2006
Firstpage
35
Lastpage
38
Abstract
This paper describes an energy-efficient 32-bit multiplier based on a modified Booth-encoding scheme in a 90-nm CMOS technology. Further power-performance and area comparisons are presented, between the proposed architecture and a conventional Wallace tree based multiplier. Simulation results shows 47 % better energy-efficiency at the same delay and 24% lower area compared to the conventional multiplier
Keywords
CMOS logic circuits; logic design; multiplying circuits; trees (mathematics); 32 bit; 90 nm; CMOS technology; Wallace tree based multiplier; energy-efficient multiplier architecture; modified Booth-encoding scheme; CMOS technology; Delay; Digital signal processing chips; Electronic mail; Encoding; Energy efficiency; Image coding; Logic; Signal processing algorithms; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Norchip Conference, 2006. 24th
Conference_Location
Linkoping
Print_ISBN
1-4244-0772-9
Type
conf
DOI
10.1109/NORCHP.2006.329239
Filename
4126942
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