• DocumentCode
    1915597
  • Title

    Configuration free SoC interconnect BIST methodology

  • Author

    Su, Chauchin ; Tseng, Wenliang

  • Author_Institution
    Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
  • fYear
    2001
  • fDate
    2001
  • Firstpage
    1033
  • Lastpage
    1038
  • Abstract
    Three-state drivers are modified to exhibit wired-logic properties in test mode. It does not only make interconnects random pattern testable but also improves the fault coverage and shortens the test length simultaneously
  • Keywords
    VLSI; application specific integrated circuits; built-in self test; design for testability; driver circuits; integrated circuit interconnections; integrated circuit testing; SoC interconnect BIST methodology; configuration free SoC interconnect testing; fault coverage improvement; random pattern testable interconnects; system on chip; systems-on-a-chip; test length reduction; test mode; three-state drivers; wired-logic properties; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design for testability; Hardware; Integrated circuit interconnections; Legged locomotion; Logic; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 2001. Proceedings. International
  • Conference_Location
    Baltimore, MD
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-7169-0
  • Type

    conf

  • DOI
    10.1109/TEST.2001.966729
  • Filename
    966729
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1915597