Title :
Configuration free SoC interconnect BIST methodology
Author :
Su, Chauchin ; Tseng, Wenliang
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
Abstract :
Three-state drivers are modified to exhibit wired-logic properties in test mode. It does not only make interconnects random pattern testable but also improves the fault coverage and shortens the test length simultaneously
Keywords :
VLSI; application specific integrated circuits; built-in self test; design for testability; driver circuits; integrated circuit interconnections; integrated circuit testing; SoC interconnect BIST methodology; configuration free SoC interconnect testing; fault coverage improvement; random pattern testable interconnects; system on chip; systems-on-a-chip; test length reduction; test mode; three-state drivers; wired-logic properties; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Design for testability; Hardware; Integrated circuit interconnections; Legged locomotion; Logic; Timing;
Conference_Titel :
Test Conference, 2001. Proceedings. International
Conference_Location :
Baltimore, MD
Print_ISBN :
0-7803-7169-0
DOI :
10.1109/TEST.2001.966729
