A Layered Approach to Estimating Power Consumption

Author

Penolazzi, Sandro ; Hemani, Ahmed

Author_Institution

Dept. of Appl. IT, Sch. of ICT, Kista

fYear

2006

fDate

Nov. 2006

Firstpage

93

Lastpage

98

Abstract

A layered approach to estimating power consumption at the highest level of abstraction is presented. This approach is sufficiently accurate and fast enough to be used as guide for exploring the algorithmic and architectural space. The layers span from use-case level down to gate level. Speed and accuracy come from our ability to relate parameterized transactions at architectural level to switching activity at gate level and to perform architecturally-aware application-level simulation for specific or sweeps of use-cases. That enables us to recreate accurately architectural-level transactions. Additionally, we use preliminary floorplan to factor physical design aspects to improve the accuracy of our estimates. We base our work on the industry standard SPIRIT for specifying IPs and platforms. Early results of work are also presented

Keywords

circuit layout; integrated circuit design; low-power electronics; IP; SPIRIT; algorithmic space; architectural space; architectural-level transactions; architecturally-aware application-level simulation; floorplan; platforms; power consumption; Algorithm design and analysis; Costs; Degradation; Design methodology; Energy consumption; Investments; Power system modeling; Process design; Space exploration; Technological innovation;

fLanguage

English

Publisher

ieee

Conference_Titel

Norchip Conference, 2006. 24th

Conference_Location

Linkoping

Print_ISBN

1-4244-0772-9

Type

conf

DOI

10.1109/NORCHP.2006.329252

Filename

4126955