A 62dB SFDR, 500MSPS, 15mW Open-Loop Track-and-Hold Circuit

In this work, the design of an open-loop front-end track & hold (T&H) circuit is considered. Advantages of the presented circuit include low power-consumption, high-speed operation, simple reliable design, and ability to operate at low power-supplies. The major problem of open-loop circuits is their relatively poor linearity. In the presented design, high linearity is achieved by applying three linearization techniques: clock boosting (Abo and Gray, 1999), resistive source degeneration (Razavi, 2001), (Ouzounov et al., 2005) and cross-coupling (Ouzounov et al., 2005), (Voorman and Veenstra, 2000). As a result, a linearity corresponding to 10-bit accuracy is achieved. The final design in a 0.18mum CMOS process achieves an SFDR of 62 dB using a sample frequency of 500 MHz while consuming 15mW at a 1.8V power supply