Effects of drain engineering on 0.35 μm NMOS Hot-Carrier degradation

The Large-Angle-Tilted-Implanted-Drain structure (LATID) has been shown to alleviate hot-carrier induced degradation in NMOSFETs. In a comparison of conventional drain, LDD and several different 0.35 μm LATID NMOSFETs we show that a reduced avalanche multiplication factor and a reduced influence of the generated interface states contribute to this improved hot-carrier reliability. The maximum supply voltage that guarantees less than 10% degradation of the transconductance in 10 years as a result of a hot-carrier stress can thus be increased from 2.7 Volts for the conventional drain and 3.3 Volts for the LDD to 4.8 Volts for the 80 keV LATID 0.35 μm NMOSFET.