DRAM Controller with a Close-Page Predictor

Author

Stankovic, Vladimir V. ; Milenkovic, Nebojsa Z.

Author_Institution

Sch. of Electron. Eng., Nis Univ.

Volume

1

fYear

2005

fDate

21-24 Nov. 2005

Firstpage

693

Lastpage

696

Abstract

Better insight of programs behavior can help in overcoming large speed difference of central processors and main memories implemented with DRAM chips. It allows us to predict required next actions, based on observed main memory access patterns, which can hide some time components in accessing DRAM memory. Authors of this paper proposed a simple dead time predictor which helps in predicting when to close the opened DRAM row. In this paper this predictor is further improved by adding a zero live time predictor. The zero live time predictor, by its essence, completes the dead time predictor

Keywords

DRAM chips; storage management chips; DRAM chips; DRAM controller; DRAM row; close-page predictor; dead time predictor; main memory access patterns; memory bank; zero live time predictor; Bandwidth; Cache memory; DRAM chips; Delay; Frequency; Performance evaluation; Pipeline processing; Prefetching; Random access memory; Semiconductor device measurement; DRAM; DRAM controller; DRAM controller policy; bank; latency; main memory; predictor; row;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer as a Tool, 2005. EUROCON 2005.The International Conference on

Conference_Location

Belgrade

Print_ISBN

1-4244-0049-X

Type

conf

DOI

10.1109/EURCON.2005.1630025

Filename

1630025