• DocumentCode
    1916016
  • Title

    A cycle-level SIMT-GPU simulation framework

  • Author

    Wang, Po-Han ; Lo, Chien-Wei ; Yang, Chia-Lin ; Cheng, Yu-Jung

  • Author_Institution
    Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • fYear
    2012
  • fDate
    1-3 April 2012
  • Firstpage
    114
  • Lastpage
    115
  • Abstract
    The massive parallelism provided by the modern graphics processing units (GPUs) makes them the attractive processors to accelerate the applications with high data-level parallelism. Therefore, the GPU architecture has recently gained a lot of attention in research community. However, the advance in the GPU architecture is impeded by the limited documents released from the major GPU vendors. Furthermore, current studies on GPUs often focus only on general-purpose (GPGPU) applications. The behaviors of the graphics applications, which are considered as the major GPU workloads, are often overlooked in these studies. A GPU design good for the GPGPU applications is not necessarily good for the graphics applications. Therefore, a simulation framework that is able to provide performance characterization for both applications is mandatory for the innovation of the GPU architecture.
  • Keywords
    circuit simulation; graphics processing units; parallel architectures; GPGPU applications; GPU architecture; cycle-level SIMT-GPU simulation framework; general-purpose applications; graphics processing units; high data-level parallelism; massive parallelism; Benchmark testing; Clocks; Computer architecture; Graphics processing unit; Libraries; Pipelines;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Performance Analysis of Systems and Software (ISPASS), 2012 IEEE International Symposium on
  • Conference_Location
    New Brunswick, NJ
  • Print_ISBN
    978-1-4673-1143-4
  • Electronic_ISBN
    978-1-4673-1145-8
  • Type

    conf

  • DOI
    10.1109/ISPASS.2012.6189213
  • Filename
    6189213