A three-step procedure utilizing only two test structures for deembedding transistor from on-wafer S-parameter measurements

This work presents a new method for de-embedding transistor characteristics from on-wafer S-parameter measurements that are affected by parasitics of a typical interconnect layout. The method is based on a six-element interconnect model and requires measuring only open and shorted dummy test structures to subtract effects of the parasitic elements in three steps. Experimental results obtained for a silicon RF bipolar transistor demonstrate validity of the method.