Combined Test Data Compression and Abort-on-Fail Testing

Author

Larsson, Erik

Author_Institution

Dept. of Comput. Sci., Linkopings Univ., Linkoping

fYear

2006

fDate

Nov. 2006

Firstpage

137

Lastpage

140

Abstract

The increasing test data volume needed for the testing of system-on-chips (SOCs) leads to high automatic test equipment (ATE) memory requirement and long test application times. Scheduling techniques where testing can be terminated as soon as a fault appears (abort-on-fail) as well as efficient compression schemes to reduce the ATE memory requirement have been proposed separately. Previous test data compression architectures often make use of multiple input signature response analyzers (MISRs) for response compression. Therefore, abort-on-fail testing and diagnostic capabilities are limited. In this paper, we propose an SOC test architecture that (1) allows test data compression, (2) where clock cycle based as well as pattern-based abort-on-fail testing are allowed and (3) diagnostic capabilities are not reduced. We have performed experiments on ISCAS designs

Keywords

automatic test equipment; data compression; integrated circuit design; integrated circuit testing; system-on-chip; ISCAS designs; abort-on-fail testing; automatic test equipment; multiple input signature response analyzers; response compression; scheduling techniques; system-on-chips testing; test data compression architectures; Automatic test equipment; Automatic testing; Clocks; Computer science; Embedded system; Fault detection; Laboratories; System testing; System-on-a-chip; Test data compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Norchip Conference, 2006. 24th

Conference_Location

Linkoping

Print_ISBN

1-4244-0772-9

Type

conf

DOI

10.1109/NORCHP.2006.329262

Filename

4126965