Hybrid BIST Scheduling for NoC-Based SoCs

Chip design is becoming increasingly communication-bound rather than computation-bound. Network-on-chip (NoC) has been proposed as one of the interconnect solutions for future systems-on-chip (SoCs). In this paper we address the test scheduling problem for such NoC-based SoCs. We assume a hybrid BIST approach, where test sets of individual cores are composed of pseudorandom and deterministic test sequences and, contrary to many other scheduling approaches, not treated as black boxes. This aspect allows finding the best ratio of deterministic and pseudorandom test sequences for the final solution. The objective of our proposed technique is to reduce the total test time by taking into account the specifics of the NoC infrastructure, while keeping the power consumption under control. Experimental results have shown the advantages of our technique for test time reduction