Title :
Error detection of arithmetic circuits using a residue checker with signed-digit number system
Author :
Wei, Shugang ; Shimizu, Kensukw
Author_Institution :
Dept. of Comput. Sci., Gunma Univ., Japan
Abstract :
An error detection method for arithmetic circuits is proposed, by using a residue checker which consists of a number of residue arithmetic circuits designed based on radix-2 signed-digit (SD) number arithmetic. Fast modulo m(m=2p±1) multipliers and binary-to-residue number converters are constructed with a binary tree structure of modulo m SD adders. The modulo m addition is implemented by using a p-digit SD adder, so that the modulo m addition time is independent of the word length of operands. Therefore, the modulo m multiplication is performed in a time proportional to log2p and an n-bit binary number is converted into a p-digit SD residue number in a time proportional to log2(n/p). The presented residue arithmetic circuits can be applied to error detection for a large product-sum circuit
Keywords :
adders; error detection; fault diagnosis; hardware description languages; logic testing; multiplying circuits; residue number systems; VHDL; arithmetic circuits; binary tree structure; binary-to-residue number converter; error detection; fast modulo multiplier; large product-sum circuit; n-bit binary number; operand word length; radix-2 signed digit number arithmetic; residue arithmetic circuits; residue checker; signed-digit number system; Arithmetic; Circuits; Electrical fault detection; Fault detection; Fault tolerant systems; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7695-1203-8
DOI :
10.1109/DFTVS.2001.966754
