Title :
Identification of undetectable faults in combinational circuits
Author :
Harihara, Mohan ; Menon, P.R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
Identification of undetectable faults is essential for preventing test invalidation due to the occurrence of such faults, and for improving the efficiency of test generation. Methods for identifying undetectable faults in combinational circuits by analyzing regions between fanout stems and reconvergent gates are presented. These methods have been successful in identifying many of the undetectable faults in several benchmark circuits, without test generation
Keywords :
combinatorial circuits; fault location; logic testing; combinational circuits; fault simulation; identifying undetectable faults; preventing test invalidation; reconvergent gates; regions between fanout stems; several benchmark circuits; Benchmark testing; Circuit analysis; Circuit faults; Circuit testing; Combinational circuits; Digital circuits; Electrical fault detection; Fault detection; Fault diagnosis; Redundancy;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63374
