Title :
Reducing power dissipation during at-speed test application
Author :
Li, Xiaowei ; Li, Huawei ; Min, Yinghua
Author_Institution :
Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Abstract :
Presents an approach to reducing power dissipation during at-speed test application. Based on re-ordering of the test-pair sequences, the switching activities of the circuit-under-test during test application can be minimized. Hamming distance between test-pairs is defined to guide test-pair re-ordering. It minimizes power dissipation during test application without reducing delay fault coverage. Experimental results are presented to demonstrate a reduction of power dissipation during test application in the range from 84.69 to 98.08%
Keywords :
automatic testing; delays; fault diagnosis; integrated circuit testing; logic testing; Hamming distance; at-speed test application; circuit-under-test; delay fault coverage; dynamic logic behavior; power dissipation; switching activities; test application; test-pair sequence reordering; Circuit faults; Circuit testing; Computers; Delay; Electrical fault detection; Hamming distance; Logic testing; Power dissipation; Switching circuits; System testing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7695-1203-8
DOI :
10.1109/DFTVS.2001.966760
