Overvoltage Protection with a CMOS-Compatible BJT

Author

Schrom, G. ; Selberherr, S. ; Unterleitner, F. ; Trontelj, J. ; Kunc, V.

Author_Institution

Inst. for Microelectron., Tech. Univ. of Vienna, Vienna, Austria

fYear

1993

fDate

13-16 Sept. 1993

Firstpage

899

Lastpage

902

Abstract

A new method of overvoltage protection in the supply path of CMOS circuits is described. The central device of the protection circuit is a CMOS-compatible npn bipolar transistor (BJT) which uses no n⁺ buried layer and can be manufactured in a simple p-well CMOS process without additional process steps. The device is especially suitable for high-voltage applications in electrically hostile environments such as automotive circuits.

Keywords

CMOS integrated circuits; bipolar transistors; buried layers; overvoltage protection; power supply circuits; CMOS circuits; CMOS-compatible BJT; CMOS-compatible npn bipolar transistor; automotive circuits; central device; electrically hostile environments; high-voltage applications; n⁺ buried layer; overvoltage protection; p-well CMOS process; protection circuit; supply path; Bipolar transistors; CMOS process; Doping profiles; Laboratories; Microelectronics; Protection; Pulse circuits; Regulators; Resistors; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 1993. ESSDERC '93. 23rd European

Conference_Location

Grenoble

Print_ISBN

2863321358

Type

conf

Filename

5435633

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1916379