Opportunities for Scaling FET´s for Gigascale Integration (GSI)

Using two- and three dimensional analytical and numerical models, scaling limits derived from small-geometry degradation of subthreshold characteristics are compared for six different FET structures in bulk Si, SOI and GaAs technologies. For Si devices, the low impurity channel MOSFET can be scaled down to L_min = 0.045μm and the dual gate SOI MOSFET to L_min = 0.028μm. The GaAs MESFET can be scaled to L_min = 0.13μm and the AlGaAs/GaAs MODFET to 0.095μm. The key physical effect which enables small values of L_min is the relative strength of the coupling between the gate and channel charge distributions.