• DocumentCode
    1916519
  • Title

    On Performance Improvement of Concurrent Applications Using Simultaneous Multithreaded Processors as NoC Resources

  • Author

    Pop, Ruxandra ; Kumar, Shashi

  • Author_Institution
    Dept. of Electron. & Comput. Eng., Jonkoping Univ.
  • fYear
    2006
  • fDate
    Nov. 2006
  • Firstpage
    191
  • Lastpage
    196
  • Abstract
    Network on chip (NoC) is a new design paradigm for building scalable multi-core/multiprocessors systems on chip (SoC) which are able to exploit the coarse grain parallelism of concurrent applications. Simultaneous multi-threaded processor (SMTP) is a superscalar processor architecture which adoptively exploits the coarse grain and the fine grain parallelism of applications, by simultaneously executing instructions from several thread contexts. In this paper, the authors make a case for using SMTPs as NoC resources and show that such a multiprocessor architecture provides better timing performances than a NoC with solely general-purpose processors (GP) or with multi-threaded processors (MTP). The authors have developed a methodology for task mapping and scheduling on a NoC with mixed SMTPs, MTPs and GPs resources, which aims to maximize the timing performances of concurrent applications and to verify their soft timing constraints. The methodology incorporates a timing analysis for estimating the response time of tasks executed in multithreaded mode of SMTPs. The experiments performed on synthetic benchmarks with average instruction parallelism of 200, have shown a maximum speedup of 2.91 for a 3times3 NoC with 9 SMTPs (4-issue, 4-multithreaded)
  • Keywords
    multi-threading; processor scheduling; system-on-chip; timing circuits; NoC resources; SMTP; SoC; coarse grain parallelism; concurrent applications; fine grain parallelism; multiprocessor architecture; multiprocessors systems on chip; multithreaded processors; network on chip; performance improvement; superscalar processor architecture; task mapping; task scheduling; timing analysis; Application software; Buildings; Concurrent computing; Delay; Design engineering; Multithreading; Network-on-a-chip; Parallel processing; Timing; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Norchip Conference, 2006. 24th
  • Conference_Location
    Linkoping
  • Print_ISBN
    1-4244-0772-9
  • Type

    conf

  • DOI
    10.1109/NORCHP.2006.329208
  • Filename
    4126979