Testing Xilinx XC4000 configurable logic blocks with carry logic-modules

Author

Sun, Xiaoling ; Xu, Jian ; Trouborst, Pieter

Author_Institution

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada

fYear

2001

fDate

2001

Firstpage

221

Lastpage

229

Abstract

This paper presents a novel built-in self-test (BIST) scheme for configurable logic blocks (CLBs) of Xilinx XC4000 field programmable gate arrays (FPGAs). The test of the dedicated carry logic module (CLM) within a CLB is included for the first time. A minimum of eight CLB test configurations is given. A centralized BIST architecture supports the single stuck-at fault test of the CLM and the whole CLB. The scheme is also capable of locating any faulty CLBs with the maximum diagnostic resolution, two adjacent CLBs

Keywords

built-in self test; carry logic; fault diagnosis; field programmable gate arrays; integrated circuit testing; logic testing; BIST scheme; Xilinx XC4000 FPGA; built-in self-test scheme; centralized BIST architecture; configurable logic blocks; dedicated carry logic module; field programmable gate arrays; single stuck-at fault test; test configurations; Built-in self-test; Circuit faults; Circuit testing; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Logic design; Logic functions; Logic testing; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on

Conference_Location

San Francisco, CA

ISSN

1550-5774

Print_ISBN

0-7695-1203-8

Type

conf

DOI

10.1109/DFTVS.2001.966774

Filename

966774