Power Analysis of Arbitration Techniques for AMBA AHB based Reconfigurable System-on -Chip

There are many directions for approaching the subject of power estimation in bus based reconfigurable SoC design. Estimating power at the low level of the SoC design abstraction has the benefit of accurate and reliable results to draw conclusion for reconfigurable integration at system level. Novelty of this work lies in the estimation of power utilized by different arbitration policies with different number of masters for reconfigurable low power designs. This will provide important information regarding the power impact of different bus arbitration policies. With this model, the designers can obtain power information in addition to the ones obtained from bus functional models when selecting different arbitration techniques driven by functional, timing and power constraints of the Reconfigurable SoC