DocumentCode
1916769
Title
Upset-like fault injection in VHDL descriptions: A method and preliminary results
Author
Velazco, R. ; Leveugle, R. ; Calvo, O.
Author_Institution
TIMA Lab., Grenoble, France
fYear
2001
fDate
2001
Firstpage
259
Lastpage
267
Abstract
Investigates an approach allowing one to evaluate the consequences of single event upset phenomena for the reliable operation of processors. The method is based on the simulation of bit flips using a modified version of a high-level circuit description. Preliminary results illustrate the potential of this new strategy
Keywords
circuit simulation; digital integrated circuits; fault simulation; hardware description languages; high level synthesis; integrated circuit reliability; integrated circuit testing; radiation effects; VHDL descriptions; bit flip simulation; ground testing; high-level circuit description; memory cells; natural radiation interaction; single event upset phenomena; space environment; upset-like fault injection; Aerospace electronics; Atmosphere; Circuit faults; Circuit testing; Costs; Error analysis; Microelectronics; Registers; Single event transient; Software testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location
San Francisco, CA
ISSN
1550-5774
Print_ISBN
0-7695-1203-8
Type
conf
DOI
10.1109/DFTVS.2001.966778
Filename
966778
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