Title :
Upset-like fault injection in VHDL descriptions: A method and preliminary results
Author :
Velazco, R. ; Leveugle, R. ; Calvo, O.
Author_Institution :
TIMA Lab., Grenoble, France
Abstract :
Investigates an approach allowing one to evaluate the consequences of single event upset phenomena for the reliable operation of processors. The method is based on the simulation of bit flips using a modified version of a high-level circuit description. Preliminary results illustrate the potential of this new strategy
Keywords :
circuit simulation; digital integrated circuits; fault simulation; hardware description languages; high level synthesis; integrated circuit reliability; integrated circuit testing; radiation effects; VHDL descriptions; bit flip simulation; ground testing; high-level circuit description; memory cells; natural radiation interaction; single event upset phenomena; space environment; upset-like fault injection; Aerospace electronics; Atmosphere; Circuit faults; Circuit testing; Costs; Error analysis; Microelectronics; Registers; Single event transient; Software testing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7695-1203-8
DOI :
10.1109/DFTVS.2001.966778
