A speed-dependent approach for delta IDDQ implementation

Author

Lee, Paul ; Chen, Alfred ; Mathew, Dilip

Author_Institution

Offshore Product Eng., LS1 Logic, Hong Kong, China

fYear

2001

fDate

2001

Firstpage

280

Lastpage

286

Abstract

IDDQ test has been widely used in the industry as a DPM (Defects Per Million) improvement tool for test coverage enhancement. It could detect random defects not caught by traditional "stuck-at-fault" functional testing. While effectiveness of traditional IDDQ test is severely affected by the large background current of deep submicron devices, several approaches have been raised on IDDQ-based methodologies to improve its fault detection sensitivity. This paper presents a new methodology based on one of the field approaches, while taking additional results of a specific test sub-circuit that monitored device speed performance into consideration. Dynamic variation due to process distribution is properly reflected via the test sub-circuit, which then leads to consistent fault detection criteria among all IDDQ measurement vectors

Keywords

CMOS digital integrated circuits; VLSI; integrated circuit testing; leakage currents; IC testing; IDDQ measurement vectors; IDDQ methodology; IDDQ test technique; VLSI circuit testing; deep submicron devices; delta IDDQ implementation; fault detection criteria; speed performance index; speed-dependent approach; sub-threshold leakage; test subcircuit; Equations; Fault detection; Fault tolerant systems; Large scale integration; Linear regression; Logic testing; Manufacturing; Monitoring; Predictive models; Production;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on

Conference_Location

San Francisco, CA

ISSN

1550-5774

Print_ISBN

0-7695-1203-8

Type

conf

DOI

10.1109/DFTVS.2001.966780

Filename

966780