DocumentCode
1916960
Title
Fast, minimal decoding complexity, system level, binary systematic (41, 32) single-error-correcting codes for on-chip DRAM applications
Author
Amir, Kazéminéjad ; Eric, Belhaire
Author_Institution
Inst. d´´Electronique Fondamentale, Univ. Paris XI, Orsay, France
fYear
2001
fDate
2001
Firstpage
308
Lastpage
313
Abstract
Fast, minimal decoding complexity, system level, binary systematic (41, 32) single-error-correcting codes for on-chip DRAM applications are presented. These (41, 32) codes allow fast single error correcting with three parity bit penalty and can be used in combinational circuits with minimal (ultimate) decoding complexity
Keywords
DRAM chips; combinational circuits; decoding; error correction codes; fault tolerant computing; binary systematic (41, 32) codes; combinational circuits; fast single error correcting; minimal decoding complexity; on-chip DRAM applications; single-error-correcting codes; syndrome decoder; syndrome generator; system level ECC; Birth disorders; Circuits; Complexity theory; Decoding; Delay; Encoding; Error correction codes; Power dissipation; Random access memory; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location
San Francisco, CA
ISSN
1550-5774
Print_ISBN
0-7695-1203-8
Type
conf
DOI
10.1109/DFTVS.2001.966783
Filename
966783
Link To Document