DocumentCode :
1917014
Title :
Sensitivity and reliability evaluation for mixed-signal ICs under electromigration and hot-carrier effects
Author :
Xuan, Xiangdong ; Chatterjee, Abhijit
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear :
2001
fDate :
2001
Firstpage :
323
Lastpage :
328
Abstract :
With the use of aggressive technologies, the reliability of analog microelectronics is attracting greater attention. In this paper, a hierarchical reliability analysis approach for analog circuits is proposed. Through the use of behavioral models, electrical stress factors at the circuit inputs are propagated top-down to sub-modules and lower-level building-block components. These stress factors are then combined with physics-of-failure models to compute the performance degradation of the circuit building-block components due to electromigration and hot-carrier effects. The degradation effects are then propagated bottom-up through the design hierarchy to compute the changes in high-level circuit specification values due to electrical stress and the expected time-to-failure. A method for "hot-spot" analysis is proposed, where a "hot-spot" is defined to be a circuit component that can most likely cause circuit reliability problems. A reliability analysis tool has been developed and preliminary results are presented
Keywords :
circuit CAD; circuit analysis computing; electromigration; failure analysis; hot carriers; integrated circuit reliability; mixed analogue-digital integrated circuits; sensitivity analysis; ASIC reliability evaluation tool; CAD reliability tool; analog circuits; behavioral models; bottom-up sensitivity analysis; circuit building-block components; degradation effects; electrical stress factors; electromigration effects; hierarchical reliability analysis; high-level circuit specification values; hot-carrier effects; hot-spot analysis; mixed-signal ICs; performance degradation; physics-of-failure models; reliability analysis tool; sensitivity evaluation; time-to-failure; top-down stress propagation; Current density; Degradation; Electromigration; Failure analysis; Hot carrier effects; Hot carriers; Integrated circuit interconnections; Microelectronics; Stress; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location :
San Francisco, CA
ISSN :
1550-5774
Print_ISBN :
0-7695-1203-8
Type :
conf
DOI :
10.1109/DFTVS.2001.966785
Filename :
966785
Link To Document :
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