Title :
Analog BIST generator for ADC testing
Author :
Bernard, S. ; Azaïs, F. ; Bertrand, Y. ; Renovell, M.
Author_Institution :
LIRMM, Univ. of Montpellier, France
Abstract :
In the context of analog BIST for A/D converters, this paper presents an implementation of an on-chip ramp generator. It is demonstrated that the proposed original adaptive scheme allows the internal generation of a highly sawtooth signal with a very precise control of the signal amplitude. In addition, the implementation of the adaptive ramp generator exhibits a very low silicon area
Keywords :
adaptive control; analogue-digital conversion; built-in self test; integrated circuit testing; mixed analogue-digital integrated circuits; monolithic integrated circuits; ramp generators; waveform generators; A/D converters; ADC testing; adaptive ramp generator; analog BIST generator; mixed signal circuits; on-chip ramp generator; sawtooth signal generation; signal amplitude control; Automatic testing; Built-in self-test; Circuit testing; Costs; Digital signal processing; Histograms; Linearity; Production; Signal generators; Silicon;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7695-1203-8
DOI :
10.1109/DFTVS.2001.966787
