Title :
Defect analysis and a new fault model for multi-port SRAMs
Author :
Nagaraj, Pradeep ; Upadhyaya, Shambhu ; Zarrineh, Kamran ; Adams, Dean
Author_Institution :
Digital Test Eng., QUALCOMM CDMA Technols., San Diego, CA, USA
Abstract :
Semiconductor memory failures depend on the behavior of its components. This paper deals with testing of defects occurring in the memory cells of a multi-port memory. We also consider the resistive shorts between word/bit lines of same and different ports of the memory. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of patterns. Not only have existing models been taken into account in our simulation but also a new fault model for the multi-port memory is introduced. The boundaries of failure for the proposed defects are identified
Keywords :
SRAM chips; failure analysis; fault simulation; integrated circuit testing; multiport networks; defect testing; electrical fault model; failure analysis; multi-port SRAM; pattern set; resistive short; semiconductor memory cell; transistor-level model; Decoding; Design for testability; Electrical capacitance tomography; Fabrication; Fault detection; Logic arrays; Microelectronics; Random access memory; Read-write memory; Testing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7695-1203-8
DOI :
10.1109/DFTVS.2001.966790
