DocumentCode
1917272
Title
Poster: The Impact of Integer Instructions in Floating Point Applications
Author
Tomari, Hisanobu ; Hiraki, Kei
fYear
2012
fDate
10-16 Nov. 2012
Firstpage
1349
Lastpage
1349
Abstract
The performance of floating-point oriented applications are determined not only by the performance of floating-point instructions, but also by the speed of integer instruction execution. Dynamic instruction trace of NAS Parallel Benchmarks (NPB) workloads show that integer instructions are often executed more than floating-point instructions in the floating-point application benchmark. Some vendors are taking the SIMD-only strategy where integer performance stays the same as generations-old ones, while floating-point application performance is increased using SIMD instructions. We show that there is a limit for this approach and that the slow integer execution has a huge impact on the per-socket NPB scores. When these performance is compared to other historic processors, we found that some of the latest processors can be improved by using the known techniques to accelerate the integer performance.
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computing, Networking, Storage and Analysis (SCC), 2012 SC Companion:
Conference_Location
Salt Lake City, UT
Print_ISBN
978-1-4673-6218-4
Type
conf
DOI
10.1109/SC.Companion.2012.180
Filename
6495963
Link To Document