A novel cascode power matching approach for high efficiency tapered traveling wave power amplifiers in SiGe BiCMOS

In this paper we present a novel cascode power matching approach for high efficiency ultra-wideband traveling wave power amplifiers using 0.25 mum SiGe HBT transistors. An inductor between the two cascode transistors increases the output impedance, the bandwidth, and the maximum output power. Design trade-offs for maximum bandwidth, gain, output power, and efficiency are discussed by means of analytical calculations and simulations. A gain of 11 dB with a gain flatness of plusmn1dB has been measured over a frequency range from 1 to 12 GHz. 19.5 dBm output power is obtained at the 1 dB compression point (P_1dB) in the desired frequency range with an associated power added efficiency (PAE) of 22.1% and a maximum OIP3 of 31.5 dBm. The power dissipation of the amplifier is 400 mW from a 5 V supply. On-chip biasing is implemented via LDO voltage reference driven by a band-gap voltage source. To the authors´ knowledge, this is the highest output power achieved by a HBT distributed amplifier in SiGe technology in this frequency range. The chip size is 2.1 mm². The experimental results agree very well with the simulated response.